1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor integrated circuit provided with a buffer circuit and a method of manufacturing the same semiconductor integrated circuit.
2. Description of the Prior Art
There is a conventional semiconductor integrated circuit provided with a bidirectional buffer circuit having a pull-up circuit.
FIG. 1 is a circuit diagram showing an example of such a conventional semiconductor integrated circuit. In this circuit, when an enable signal B is at a low level, a control circuit 701 outputs low-level output signals EI and EIN in response to a high-level input signal A, whereas high-level output signals EI and EIN in response to a low-level input signal A. On the other hand, when the enable signal E is at a high level, the control circuit 701 outputs a high-level output signal EI and a low-level output signal EIN, irrespective of the input signal level.
A PMOS transistor 703 and an NMOS transistor 704 constitute an output buffer circuit 702 that is connected to the control circuit 701. When the low-level output signal EI of the control circuit 701 is applied to the gate of the PMOS transistor 703, the PMOS transistor 703 is turned on, so that a supply potential supplied to the source of the transistor 703 is applied to an output terminal 707. On the other hand, when the output signal EI of the control circuit 701 is at the high level, the PMOS transistor 703 is turned off. In contrast with this, when the high-level output signal EIN of the control circuit 701 is applied to the gate of the NMOS transistor 704, the NMOS transistor 704 is turned on, so that a ground potential is applied to the output terminal 707. On the other hand, when the output signal EIN of the control circuit 701 is at the low level, the PMOS transistor 704 is turned off.
Further, in FIG. 1, a PMOS transistor 705 acts as a pull-up circuit 705. Here, since the gate of the PMOS transistor 705 is grounded, this PMOS transistor 705 is always kept turned on, so that a supply potential supplied to its source is always applied to the output terminal 707.
Further, an input buffer circuit 706 outputs a signal inputted through the output terminal 707 to internal circuitry (not shown) of the semiconductor integrated circuit.
In the above-mentioned conventional integrated circuit, when the enable signal E is at the low level and when the input signal A is at the high level, since the output signal of the output buffer 702 changes to the high level, the output terminal 707 changes also to the high potential level. Further, when the enable signal E is at the low level and when the input signal A is also at the low level, since the output signal of the output buffer 702 changes to the low level, the output terminal 707 changes also to the low potential level. On the other hand, when the enable signal E is at the high level, although the output of the output buffer 702 is not decided, since being pulled up by the PMOS transistor 705, the potential at the output terminal 707 is kept at the high level.
In the above-mentioned conventional semiconductor integrated circuit provided with the buffer circuit shown in FIG. 1, however, even when the output signal of the output buffer circuit 702 is at the low level, the PMOS transistor 705 is always kept turned on. There exists a problem in that current flows from the supply potential connected to the source of the PMOS transistor 705 to the ground through the two turn-on MOS transistors 705 and 704. This through current increases power consumption of the semiconductor integrated circuit.